1. Field of the Invention
This invention relates generally to displays, and in particular to the provision of the voltages required for modulation to individual pixels on pulse width modulated displays.
2. Background
Pulse width modulated displays comprise a significant component of modern display technologies. Plasma display panels (PDPs) and DLP digital micromirror devices (DMD) are two common examples. Some liquid crystal technologies use analog gray scale. Thin film transistor (TFT) displays using analog gray scale techniques are found both in direct view LCDs and in transmissive LCDs used for projection applications. Liquid crystal on silicon (LCOS) displays have been developed for near to eye applications and for projection applications using both these modulation methods. As the concepts and construction of LCOS displays are well known in the art no detailed description is provided.
One early example of a pulse width modulated LCOS display in which the full range of voltage needed to modulate the liquid crystal is provided is presented in Potter et al, “Optical correlation using a phase-only liquid crystal over silicon spatial light modulator”, SPIE Vol 1564, pp. 363-372, 1991. (See especially paragraph 4.) FIG. 1A presents a drawing of the prior art pixel and FIG. 1B presents the relationship between the logic states of the LCOS device, the node voltages and the drive voltages delivered to the liquid crystal cell. The limitation of the approach taken in Potter is that the drive rail voltages of the silicon backplane are the only voltages that can be delivered to the individual device pixels, there being no means provided to provide other voltages to the individual pixels.
The prior art pixel is constructed as follows. The pixel circuit 150 comprises a memory element 152 (described as a 6T SRAM memory cell), an XNOR gate 154 (described as a 4 transistor element), and a pixel mirror 156. The memory element 152 is connected to the XNOR gate 154 at node A 158. The XNOR gate 154 is connected to the pixel mirror at node B 160. The XNOR gate is also connected to a universal clock signal 184 at node 168. The liquid crystal cell (not shown) is formed by an array of pixel circuits 150 covered by a counter electrode 170 with a suitable liquid crystal 172 and alignment layers (not shown) in between. The counter electrode voltage is determined by a voltage-conditioning network formed of two resistors 180 and 182 of the same resistance and a capacitor 178. The network is driven at node D 164 by a signal VD that is in phase with the universal clock signal 184 but which may possess a different voltage amplitude as needed to achieve the required offset voltage at counter electrode 170 to drive the liquid crystal cell. The circuit formed by the resistors 180 and 182 when placed between voltage VB 182 and ground form an offset DC bias of ½VB. The capacitor asserts the AC component of the clock signal VD on the DC bias voltage to create a switching voltage in phase with the universal clock 184 but of a different magnitude. The pixel voltage for each pixel is in phase with the universal clock when the memory cell is loaded with 1 and is out of phase when the memory cell is loaded with 0. The liquid crystal voltage state at an individual pixel follows the rules shown in FIG. 1B.
As is well known in the art, a semiconductor device may be designed to operate over a range of voltages but the range can be limited by other considerations such device operating speed and device heating contributions. These considerations have become more important as semiconductor technology has advanced into finer design rules. Means to break the link between the operating range of the semiconductor device and the liquid crystal cell pixel voltages have been developed to address these issues.
One prior art invention which overcomes some limitations to the use of the semiconductor drive voltages is described in U.S. Pat. No. 6,005,558, Hudson et al, as shown in FIG. 2. FIG. 2 shows a block diagram of an exemplary pixel circuit 250 of a display (not shown) to include a memory storage device 252 and a multiplexer 254. Memory storage device 252 includes complementary input terminals 264 and 266, coupled to data lines (BPOS) 290 and (BNEG) 292, respectively, an enable terminal 258 coupled to word line 262, and a data output terminal 260. Responsive to a write signal on word line 262, memory storage device 252 latches the data bit on output terminal 260. Memory storage device 252 is a static-random-access (SRAM) latch in this example.
Multiplexer 254 includes a first input terminal 297 coupled to first voltage supply terminal (V1) 294, a second input terminal 298 coupled to second voltage supply terminal (V0) 296, an output terminal 299 coupled to pixel electrode 256 (a pixel mirror in this particular embodiment), and a control terminal 268 coupled to output terminal 260 of memory storage device 252.
Thus configured, multiplexer 254, responsive to the data bit asserted on its control terminal 268, is operative to selectively couple pixel electrode 256 with first voltage supply terminal (V1) 297 and second voltage supply terminal (V0) 298. For example, if a bit having a logical high value (e.g., digital 1 or 5 volts) is stored in memory storage device 252, then multiplexer 254 will couple pixel electrode 256 with first voltage supply terminal 297. On the other hand, if a bit having a logical low value (e.g., digital 0 or 0 volts) is stored in memory storage device 252, then multiplexer 252 will couple pixel electrode 256 with second voltage supply terminal (V0) 298.
The use of the data bits stored in memory 252 as a control means allows the pixel electrodes to be driven with digital voltages differing from the voltages used to drive the logic circuitry of the display. As another example, off states (0 volts across a pixel cell) can be asserted on the entire display at one time without changing any of the data stored in the latches of the display. Inspection of FIG. 2 reveals that the pixel is incapable of achieving DC balance without the rewriting of data unless the voltage lines V1 294 and V0 296 are voltage modulated. Static voltages cannot be applied to those line and achieve this. The text of '558 describes the use of a multiplexer external to the cell to deliver these voltages.
Notwithstanding the advantages offered by the use of liquid crystal drive voltages that are independent of the semiconductor supply voltages, the requirement to take extra voltage supply lines across the display surface will lead to a decrease in overall semiconductor yield due to added opportunity for critical defect placement and also adds significantly to the design layout process because space must be found across the entire pixel array for supply lines to allow these added voltages to be asserted uniformly. It is against these competing requirements for performance and simplicity that the present invention is conceived.